A 1v 31 Dbm Iip3 Reconfigurable Continuously Tunable Poweradjustable Activerc Lpf

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Multi-Mode, Multi-Band Active-RC Filterand Tuning Circuits for SDR Applications

Published: April 1st, 2010

DOI: 10.5772/8628

Kang-Yoon Lee*
- Konkuk University, Republic of Korea

*Address all correspondence to:

1. Introduction

The prevalence of wireless standards and the introduction of dynamic standards/ applications, such as software-defined radio, necessitate filters with wide ranges of adjustable bandwidth/power, and with selectable degrees and shapes. The baseband filters of transceivers often utilize a significant portion of the power budget, especially when high linearity is required. Likewise, a widely tunable filter designed for its highest achievable frequency consumes more power than necessary when adjusted to its lowest frequency. Because power consumption is proportional to the dynamic range and frequency of operation, power-adjustable filters have recently gained popularity, as they can adapt their power consumption dynamically to meet the needs of the system.

Dynamic variation in filter attributes (e.g. frequency, order, type) coupled with companies' desire to reuse IP has popularized highly programmable filters. The lowpass-filter cutoff frequencies of several wireless/wireline standards are within the 1–20 MHz frequency range. Many of these standards are irregularly spaced in frequency and do not lend themselves well to standard binary-weighted resistor arrays. In previous designs frequency is solely controlled digitally, and hence, digital circuitry or an ADC is used to tune the frequency of the filters. Gm–C filters offer continuous frequency tunability and can operate at higher frequencies than their active-RC counterparts. MOSFET-C filters can also provide continuous frequency tuning, but both Gm–C and MOSFET-C filters lack good linearity. MOSFET-C filters additionally suffer from reduced tuning range at lower supply voltages; also, in MOSFET-C most of the voltage drop occurs over nonlinear MOSFET triode resistors, which appreciably degrades its linearity. Along these lines, filters with good linearity have been developed that tune on the basis of duty-cycle control in switched-R-MOSFET-C filters; however, duty-cycle control by nature necessitates a discrete-time filter. Active-RC filters, known to have good linearity, have been used for continuous-time programmable filters. Some such filters have narrow frequency ranges, with a few others providing wider but solely discrete ranges. Purely discrete switched resistor tuning limits filter frequency tuning to discrete frequencies determined by the overall frequency range and number of bits used. Tuning to different frequency bands precisely would require very fine resistor stripes to meet precision requirements for the low-frequency end.

Newer technologies offer increased integration with smaller feature sizes, allowing the filter to be on the same chip with other transceiver blocks. This integration especially promotes reconfigurable architectures, as DSPs can be integrated with the transceiver and can control the mode of operation. However, as minimum feature size shrinks, supply voltages also reduce, which complicates classical linearization techniques of Gm–C filters. In this respect, active-RC filters possess an intrinsic linearity advantage.

The third generation standards will create a demand for cellular phones capable of operating both in the new wideband and in the existing narrower band systems. Second generation system has a channel bandwidth in range of tens of kilohertz, whereas channel bandwidths of wideband systems are in megahertz range. So the corner frequency of an analog channel select filter must be tunable over at least a decade of frequency. This will increase the power consumption and the area. The proposed multi-mode baseband filter can minimize the area and optimize the power consumption by sharing the capacitors and resistors. And new tuning method can reduce the number of switches in programmable capacitor arrays which can be dominant noise sources.

This chapter is organized as follows. In Section 2, the multi-mode, multi-band active-RC filter architecture is described. Section 3 describes filter tuning circuits. Section IV shows experimental results from a 0.35 m CMOS implementation and Section V concludes the paper.

2. Multi-mode, multi-band active-RC filter architecture

2.1 Multi-mode, multi-band active-RC low-pass filter

Figure 1.

a) Resistor matrices and capacitor matrices (b) schematic of the baseband filter.

Figure 1 shows the designed active-RC 5^th-order Chebyshev filter. Resistor matrices and capacitor matrices are shown in Figure 1(a). Resistor matrics are composed of resistors and switches. Switches are controlled by Mode_sel(3:0), as defined in Table 1. Resistor for WCDMA is not connected to any switch.

The bandwidths of PDC, GSM, IS-95, and WCDMA are 13 kHz, 100 kHz, 630 kHz, and 2.1 MHz, respectively. Mode_sel(3:0) bits are set through the serial interface and represented in thermometer code. The corner frequency was made tunable by using programmable capacitor matrices. Capacitor matrices are composed of capacitors and switches. The control bits required for each mode are 2-bits. Thus, total number of 8-bits are required. The tuning bits, cont(7:0) are determined from the on-chip tuning block based on the mode. In PDC mode, the low corner frequency leads to large passive components occupying a lot of die area [2]. Because the capacitor matrices dominate the area, capacitors were shared between modes. There are trade-offs between resistor values and capacitor values. When resistor values are reduced to make thermal noise small, capacitor values become large. That leads to a large area. On the other hand, as capacitor values become smaller to reduce the area, the noise level rises. So, capacitor values and resistor values were optimized.

Mode_sel(3:0)	Standard	Bandwidth
"0001"	PDC	13 kHz
"0010"	GSM	100 kHz
"0100"	IS-95	630 kHz
"1000"	WCDMA	2.1 MHz

Table 1.

Mode definition and corresponding bandwidths.

2.2. Tunable active-RC complex band-pass filter

Figure 2 shows the Adjacent Channel Interference (ACI) of the PHS system. The nearest interferer is located at 600 kHz, and its magnitude is 50 dB larger than the wanted signal.

Figure 2.

Characteristic of (a) Lowpass Filter in Direct-Conversion Receiver (b) Complex Bandpass Filter in Low-IF Receiver.

As shown in Figure 2(a), if the direct conversion receiver architecture is used, the interferences are located at 600 kHz, which can be attenuated by the lowpass filter. However, if the IF frequency is 150 kHz, the interferences are shifted to -450 kHz, +750 kHz, respectively as shown in Figure 2(b). If the lowpass filter is used, the attenuation characteristic is tighter because the worst case interferer is seemed to be located at 450 kHz. Therefore, the complex bandpass filter whose center frequency is located at 150 kHz is designed for the ACS performance.

The transfer function of the complex bandpass filter is found by frequency translating a low-pass filter.

H b p ( j ω ) = H l p ( j ω − j ω c )

The translation of a single pole is given in Eq. (2) and (3)

H l p ( j ω ) = 1 1 + j ω / ω o

H b p ( j ω ) = 1 1 − j ω c / ω o + j ω / ω o = 1 1 − 2 j Q + j ω / ω o

A single complex pole cannot be realized with a real filter. Only complex pole pairs can be realized. The result of Eq. (2) is a single complex pole. The translated version of a single complex pole is also given with Eq. (3). The complex part must just be added to or subtracted from the complex term 2 j Q .

Figure 3.

Block scheme for the realization of a single complex pole.

The realization of for a single pole is given in Figure 3. It is nothing more than the direct synthesis of the transfer function. Figure 3 is the full block schematic with building blocks for real signals.

Figure 4(a) shows the designed 3rd-order Chebyshev complex bandpass filter. The wanted signal is composed of the in-phase signal and quadrature signal, which are separated by the 90 phase. Complex bandpass filter uses both signals to perform the complex operations. As shown in Figure 4(a), the complex bandpass filter has the in-phase signal path and the quadrature-phase signal path. Internal nodes of each paths are inter-connected to other paths. Therefore, I/Q mismatches is one of the most critical design issues in the complex filter. In this design, because I/Q mismatch compensation scheme is applied, I/Q mismatch is drastically reduced.

Figure 4.

a) Schematic (b) resistor arrays (c) capacitor arrays of the complex bandpass filter

Resistor arrays and capacitor arrays are shown in Figure 4(a). Resistor arrays are composed of resistors and switches. Resistor arrays control the center frequency of the bandpass filter and its control signals, rconti(6:0), rcontq(6:0), are set through the serial interface and represented in thermometer code.

The corner frequency was made tunable by using programmable capacitor arrays. Capacitor arrays are composed of capacitors and switches. The tuning bits, ccont(1:0), are determined from the on-chip tuning block. There are trade-offs between resistor values and capacitor values. When resistor values are reduced to make thermal noise small, capacitor values become large. That leads to a large area. On the other hand, as capacitor values become smaller to reduce the area, the noise level rises. So, capacitor values and resistor values were optimized.

3. Tuning circuit of active-RC filter

Resistors and capacitors are usually varied about 15% due to the process variation. In continuous time filters, this leads to a large variation of the corner frequency, which in most case, must be compensated by adjusting the component values.

Conventional full analog tuning circuit based on VCO is shown in Figure 5(a). However, this tuning circuit is not suitable to tune an active-RC filter with programmable capacitor matrices. The output of the loop filter in the PLL is analog voltage, which cannot be interfaced directly with the capacitor matrices.

On the other hand, too many digital bits are required for fine resolution in the conventional full digital circuit shown in Figure 5(b). Thus, the area and noise level are too high due to many number of switches and capacitor matrices.

Figure 5.

a) Full analog tuning method (b) Full digital tuning method.

The concepts of the full analog, full digital and proposed two-step tuning method are shown in Figure 6(a), (b) and (c), respectively.

The block diagram of the proposed two-step tuning scheme is shown in Figure 7. The clock generator provides the clocks, clk0, clk1 to coarse and fine tuning controllers. C_tu is charged during clk0 is high, and VCOMP is sampled by clk1. Reference voltages for comparators, Vref, Refl, RefH, RefM are generated in the reference voltage generator block. The operation is as follows. Before main capacitor tuning steps, the reference tuning loop is enabled to

Figure 6.

Concept of (a) full analog tuning method (b) full digital tuning method (c) proposed two-step tuning method.

Figure 7.

Block diagram of the proposed two-step tuning method.

compensate the resistor variation. Pbias is compared with Vref, and vres(2:0) is controlled according to the result. When pbias is larger than Vref, resistor load should be smaller, so vres(2:0) is increased. On the other hand, if pbias is smaller than Vref, resistor load should be larger, so vres(2:0) is decreased. Reference tuning is completed when pbias crosses the Vref.

After the reference tuning, main capacitor tuning is done in two-steps, that is, the coarse tuning and the fine tuning.

Figure 8 shows the timing diagram of the proposed two-step tuning method.

Figure 8.

Timing diagram of the proposed tuning method.

Figure 9.

a) Block diagram (b) timing diagram of the replica filter in coarse tuning block.

Figure 9 shows the block diagram and the timing diagram of the replica filter in the coarse tuning block. When VCOMP voltage is precharged when clk0 and clk1 are high. When clk0 goes from high to low, the VCOMP voltage is determined as Equation 4.

V C O M P = V c o m − 1 R C t u ( V r e f _ c t − V c o m ) T

First, CCONT(1:0) are tuned until VCOMP is located between pre-determined ranges. VCOMP is compared with refL and refH. When VCOMP is higher than refH, CCONT(1:0) are increased. Whereas, if VCOMP is lower than refL, CCONT(1:0) are decreased. When VCOMP is located between refL and refH, coarse_Lock signal goes from low to high. Usually, many tuning capacitance levels are required for fine resolution. But, only two bits are sufficient in this design with the two-step tuning method. After the coarse_lock signal is asserted, the corner frequency is tuned by the fine tuning control block.

Fbias controls the tail current of the op-amp. Thus, the DC-gain of the op-amp is changed according to the Fbias voltage. If the DC-gain of the op-amp is infinite, the cut-off frequency does not change. However, because the DC-gain of the op-amp is finite, the cut-off frequency of the filter is changed as the DC-gain of the op-amp changes. Fbias is compared with refM. When VCOMP is larger than refM, Fbias should be increased. On the other hand, Fbias should be decreased when VCOMP is smaller than refM. The range of Fbias is 0.8 V to 1.2 V. The bandwidth of the op-amp is adjustable according to the mode to save the power. And the transistor sizes in the op-amp are designed to be very large to reduce the 1/f noise.

4. Experimental results

4.1. Multi-mode, multi-band active-RC low-pass filter

The multi-mode, multi-band active-RC low-pass filter was fabricated using a 0.35 m CMOS process. The chip area is 3.8 mm² and the supply voltage is 3 V.

Figure 10.

Amplitude response of the filter in WCDMA mode.

Figure 10 shows the amplitude response of the filter in WCDMA mode at every code. The cut-off frequency is 2.1 MHz in WCDMA mode. The current consumptions are 5.2 mA, 6.1 mA, 7.1 mA, and 8.4 mA, respectively. The current in PDC mode is less than that of WCDMA mode because the gain and the bandwidth of the op-amp are smaller in PDC mode. The frequency tuning range is from 10 kHz to 3MHz. Out-of-band IIP3 was determined by performing IM3 test. In PDC mode, when two tones of +15 dBm at 20 kHz and 30 kHz are applied, IM3 is –77 dBm. In WCDMA mode, out-of-band IM3 is –68 dBm, when two tones of +14 dBm at 1.8 MHz and 3.0 kHz are applied. Input-referred average passband noise densities of the filter are 250, 130, 85, and 54 n V / H z for PDC, GSM, IS-95, and WCDMA, respectively. The passband ripple is less than 0.5 dB in all modes. The stopband rejections are 79, 79, 75, and 75 dB for PDC, GSM, IS-95, and WCDMA, respectively. Table 2 summarizes the performance of the filter.

Technology	0.35 m CMOS
Chip area	3.8 mm 2
Supply voltage	3 V
Tuning range	10 kHz ~ 3 MHz
	PDC	GSM	IS-95	WCDMA
Current (mA)	5.2	6.1	7.1	8.4
IIP3 (dBm)	28	25	23	21
Noise ( n V / H z )	250	130	85	54
Passband ripple	0.5	0.5	0.5	0.5
Stopband rejection	79	79	75	75

Table 2.

Performance summary.

4.2. Tunable active-RC complex band-pass filter

The complex bandpass filter was fabricated using a 0.35 m CMOS process. The chip area is 3.8 mm². The supply voltage is 3 V. Figure 11 shows the microphotograph.

Figure 12 shows measured amplitude response of the complex baseband filter, when the temperature is changed from -10C to 60C. The cut-off frequency is 150 kHz 110 kHz. The cut-off frequency is almost constant as the temperature is changed due to the proposed filter tuning method.

Figure 12.

Measured amplitude response of the complex bandpass filter.

The power consumption is 13 mW. The frequency tuning range is 100 kHz, which is the 50% of the signal bandwidth. That is, the cut-off frequency can be adjusted by 100 kHz although it is shifted due to the temperature, the supply voltage, and the process variations.

Out-of-band IIP3 was determined by performing IM3 test. When two tones of -44 dBm at 600 kHz and 1.2 MHz are applied, IIP3 is +25 dBm.

Input-referred average passband noise density of the filter is 85 n V / H z . The passband ripple is less than 0.8 dB, and the stopband rejection at -450 kHz is 66 dB. Table 3 summarizes the performance of the filter.

Technology	0.35 m CMOS
Chip area	3.8 mm 2
Supply voltage	3 V
Tuning range	100 kHz
Power (mW)	13
IIP3 (dBm)	25
Noise ( n V / H z )	85
Passband ripple	0.8

Table 3.

Performance summary.

5. Conclusion

The CMOS multi-mode, multi-band low-pass filter and complex baseband filter are presented. Capacitors and resistors were shared to minimize the area. Proposed two-step tuning method can reduce the number of switches and thus, can reduce the noise and the area.

References

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Published: April 1st, 2010

© 2010 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike-3.0 License, which permits use, distribution and reproduction for non-commercial purposes, provided the original is properly cited and derivative works building on this content are distributed under the same license.

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Source: https://www.intechopen.com/chapters/9845

A 1v 31 Dbm Iip3 Reconfigurable Continuously Tunable Poweradjustable Activerc Lpf

Multi-Mode, Multi-Band Active-RC Filterand Tuning Circuits for SDR Applications

Kang-Yoon Lee*

1. Introduction

2. Multi-mode, multi-band active-RC filter architecture

2.1 Multi-mode, multi-band active-RC low-pass filter

Figure 1.

Table 1.

2.2. Tunable active-RC complex band-pass filter

Figure 2.

Figure 3.

Figure 4.

3. Tuning circuit of active-RC filter

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

4. Experimental results

4.1. Multi-mode, multi-band active-RC low-pass filter

Figure 10.

Table 2.

4.2. Tunable active-RC complex band-pass filter

Figure 11.

Figure 12.

Table 3.

5. Conclusion

References

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